The questions asked in the online test of the company **ARM Holdings** which is a **VLSI semiconductor and software** design company. They conduct online tests through **hirepro**. Data analysis, Problem-solving, and Puzzle questions were there in the aptitude section.

They focused mainly on **MOSFET** and **CMOS** technology. In that, they asked about CMOS circuits, MOSFET physics, and Digital electronics-related questions.

Here are the few memory-based questions of the ARM holdings company. Refer to these questions and excel in your preparation level for the online test of ARM holdings.

1. What is the **transit time of the MOSFET**, if it has a **channel length of 180 nanometers** and is Given Vds = 3V and un 750cm^2/V-sec?

**Options**

1. 144 fS

2. 155 fS

3. 166 fS

4. 133 fS

2. **Five input NOR and NAND gates** are designed with **W/L** width by the length of all the transistors are given by **10/1.** What are the equivalent (W/L)n and (W/L)p of NAND and NOR gates respectively?

**Options**

1. 3/1 and 11/1

2. 4/1 and 20/1

3. 2/1 and 10/1

4. 5/1 and 9/1

3. For an **enhancement type MOSFET**, Given the current **ID(on) = 325 mA** and the gate to source voltage **Vgs(on) = 12V.** If the **drain current ID for Vgs = 7V is 87.62 mA**. What are the values of the **proportionality constant K** and **threshold voltage Vth**? Note: The Vth was observed to be less than 6V.

**Options**

1. K = 3 mA/V^2 and Vth = 1.6 V

2. K = 4.36 mA/V^2 and Vth = 5 V

3. K = 3.5 mA/V^2 and Vth = 2 V

4. K = 4 mA/V^2 and Vth = 2.5 V

4. How a **depletion-mode NMOS** can be turned OFF? Vg = gate voltage and Vth = the threshold voltage.

**Options**

1. By applying Vg greater than 0 V

2. By applying Vg less than Vth but Vg greater than 0 V

3. By applying Vg greater than Vth

4. By applying Vg less than -Vth

5. For an **n-channel enhancement MOSFET**, given u = u0, e = e0, the **channel width W is 1 mm**, the **dielectric thickness is 1 nm**, what is the value of the **proportionality constant k**? Note: u is mobility and e is epsilon(permeability).

**Options**

1. K = 5.56 mA/V^2

2. K = 11.12 mA/V^2

3. K = 23.41 mA/V^2

4. K = 17.28 mA/V^2

6. For the below circuit shown, if the **input frequency is 4.35GHz**. Find the **output frequency.**

**Options**

1. 8.7 GHz

2. 4.35 GHz

3. 1.085 GHz

4. 2.175 GHz

7. A **resistance equivalent model** of the CMOS circuit is shown below. If **R1 = 0.5 kOhm, R2 = 20kOhm, VSS = 5V,** then what is the output voltage Vo for 0-state?

**Options**

1. 4.88 V

2. 0 V

3. 0.122 V

4. 0.125 V

8. For CMOS circuits calculate the **third-order input intercept point.** If the **transconductance** **gm is 30u** and **first-order** and **second-order** gm is 1u and 0.5u respectively.

**Options**

1. 19 dB

2. 22 dB

3. 36 dB

4. 8 dB

9. To construct the source and drain of the nMOS, the substrate is doped with a carrier concentration of 10^18/cm^3. If the source and drain junction built-in potential is 0.72 V. Then calculate the depth of the junction depletion region.

**Options**

1. 30 um

2. 10 um

3. 50 um

4. 70 um

10. Calculate the value of the a.c. output voltage of the following **amplifier** by considering the Idss = 15 mA, Vin = 400 mV, and gm = 3.5 ms.

**Options**

1. 703.2 mV

2. 806.4 mV

3. 600.9 mV

4. 905.3 mV

Below are the interview questions that are asked in an online test of **Qualcomm.** These are only memory-based questions, try to prepare these kinds of questions to clear the **Qualcomm interview written test**.

The written test will be of **60minutes**, which consists of the **aptitude section**, the **C programming** section, and the **technical electronic** section. The given **time** won’t be sufficient to solve all the questions so solve very fast and with great **accuracy.**

The **digital electronics** section questions were as below

1. The circuit shown below is used as the

**Options**

1. full adder

2. half adder

3. full subtractor

4. half subtractor

2. A **dynamic RAM** with a **storage capacitance** of C = 1uF which can hold a charge of 10uC is **refreshed every 12.5msec**. What is the discharge **current** and **voltage** of the capacitor?

**Options**

1. I = 0.8 mA current and V = 10 volts voltage

2. I = 1 mA current and V = 5 volts voltage

3. I = 1.25 mA current and V = 12 volts voltage

4. I = 1 mA current and V = 6 volts voltage

3. What is the **SNR signal-to-noise** ratio of a **16 bit ADC** analog to the digital converter?

**Options**

1. 75

2. 86

3. 98

4. 67

4. Consider the boolean equation given below: **F = ABCD’ + A’B’CD + AB’C’D + A’B’C’D’** . Write a minimum sum of products or min. **SOP** without don’t cares using **Karnaugh** map.

**Options**

1. A’B’ + A’B’C’D’ + CD

2. A’B’ + AB’C’D + ABCD’

3. A’B’ + AB’C’D’ + ABCD’

4. AB’ + A’B’C’D’ +CD

5. Find the **next state output** Qn+1 of the given circuit below.

**Options**

1. XQ’ + (X+Q)

2. X’Q’+XQ

3. X+Q

4. XQ

6. Find the output of the **flipflop** with input J and K. J = J1J2J3 and K = K1K2K3. Ans assume initially Q = 0.

J1 = 1011011

J2 = 0111010

J3 = 1111000

K1 = 0001110

K2 = 1101100

K3 = 1010101

**Options**

1. 0010110

2. 0011000

3. 0110110

4. 0110010

7. A **modulo 50** counter can be implemented using

**Options**

1. 5 modulo 10 counters

2. 10 modulo 5 counters

3. 10 modulo 10 counters

4. modulo 10 counter followed by modulo 5 counter

8. Find the **number of 8 to 1 multiplexers** required to realize a **32 to 1 multiplexer.**

**Options**

1. 4

2. 5

3. 6

4. 8

9. The instruction **move AX, [CX]** indicates which kind of **addressing** mode?

**Options**

1. Direct addressing mode

2. Register indirect addressing mode

3. Immediate addressing mode

4. Register relative addressing mode

10. Convert the following decimal value into the binary value **(112)d = ( )2**?

**Options**

1. (0000011)2

2. (0011011)2

3. (1110000)2

4. (0001100)2

11. Which one of the given options is the same as the **NOT-AND gate**?

**Options**

1. XNOR

2. NOR

3. NAND

4. NOT

12. Which one of the given options is the **minimum number of AND gates** required for the below-given logic function?

PZ + NZ

**Options**

1. 0

2. 1

3. 2

4. 3

13. Which one of the given options is the **correct reduced expression** for the below-given logic function?

(P + Y).(P’ + Y)

**Options**

1. 0

2. Y

3. P

4. P’ + Y

14. What will be the value produced if the number given below is** left-shifted once?**

11010011

**Options**

1. 10100110

2. 11100110

3. 10100111

4. 00110110

15. In **8086,** If data stored in the **AX register is 03H** then what will be the content of the **AX register after executing** the following instructions.

`OR AX,09H`

`AND AX,AAH`

`XOR AX,FFH`

`NEG AX`

`NOT AX`

**Options**

1. FCH

2. F5H

3. F4H

4. 03HIf

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