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Synopsys VLSI Interview Questions – 2020

Synopsys VLSI Interview Questions - 2020
The placement experience with Synopsys and the questions asked in the Synopsys VLSI interview are listed. The interview happened on the college campus of NIT (National Institute of Technology). The interview process had a written test followed by the interview round.

Synopsys written test:

The written test was conducted for a duration of 120 minutes which had a total of 65 questions.

The written test included four sections in which there were 10 aptitude questions which were easy levels.

And a section of Digital Electronics questions which consisted of a total of 25 questions.

An Analog section with 20 questions 20 marks and of course there was a programming section that had C, C++, and Verilog programming questions a total of 10 questions with 10 marks.

Aptitude section

In the aptitude section, the questions were based on the Remainder theorem, Geometry, Probability, Permutations, and Combinations, Shake hand-based problems, and direction-based questions (East, West, North, and South).

If each of the persons is shaking hands with every other person only one time. If there are five persons, the total number of handshakes will be ____?.

Digital section

In the digital section, the questions were based on topics such as Two’s complement addition, Pass Transistor Logic, Counters, the Sequence detector circuit design (pattern 1-3-5-7) was given, and asked what are the total number of flipflops required to design.

Microprocessor-based questions were also there.

A mod 1024 counter was given with an input with frequency fin 1MHz what is the output frequency fout.

The network theory questions such as based on the quality factor, series RLC circuits, and LPF low pass filter questions were asked. So my advice is to go through complete gate-level study materials.

Design XOR gate using 2 to 1 mux. Two network circuits including resistor, voltage source, and diode in it (using KCL they can be solved).

A circuit to calculate equivalent resistance. Noise Margin VIL and VIH.

The closed-loop gain of the OP-Amp circuit.

What is a Recursive function?. A triangular input waveform was given to an Op-Amp differentiator.

Voltage transfer characteristics of CMOS inverter and Peak inverse voltage of half-wave and full-wave rectifier circuits.

Analog Section

In the analog section, Go through the Razavi book completely. Solving Diode-based and NPN and PNP BJT transistor-based problems will be a good advantage. Calculating the voltage in MOSFET amplifier circuits.

Finding the base current in the NPN transistor is one of the questions. Current mirror and Differential amplifier voltage gain, if you go through the first five chapters of Razavi it will be fine.

Synopsys Interview Round

In the interview round the first question, they asked was my self-introduction.

1. Then they asked questions based on designing Frequency dividers using the Johnson counter that too an efficient design with different duty cycles.

2. Modulo counters and number of required flip-flops to design those counters.

3. To write the C or Verilog program of the designed frequency divider circuit. Next, Immediately they asked to tell the difference between Blocking and Non-blocking assignments.

4. STA Static timing analysis and setup time and hold time. How metastability occurs.

5. C++, OOPs concepts, and Python, DMA controls, and FIFO depth calculation. The branch and specialization related questions such as

Why you chose VLSI System being from an electrical background?
Why you chose Synopsys?
How much you know about us?
What are the different Synopsys tools you use in VLSI?

Mtech project and BTech project and then, my hobbies were asked.

My advice is to focus more on the basics and on the above-listed topics. Prepare well on all gate subjects because the written test questions were Gate level.

Also, go through,

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