The FIFO depth calculation made easy(use synchronizers) is the most asked question in the interviews and a very important topic any VLSI or Electronics engineer must know. When we want to establish a connection between two different asynchronous clock blocks a common option is to use synchronizers.

Here the term asynchronous clock domain refers to the blocks of circuits which do not share a common single clock. Let us understand how the connection can be established between them.

Table Of Contents

- Synchronizers
- FIFO
- case1 fx > fy, no idle clocks
- case2 fx > fy, one idle clock
- case3 fx > fy, one and three idle clocks
- case4 fx < fy, no idle clocks
- case5 fx < fy, one and three idle clocks
- case6 fx = fy, no idle clocks
- case7 fx = fy, one and three idle clocks
- A typical example problem1
- A typical example problem2

## Synchronizers

As shown in the above figure the system is controlled by clock A and system B is controlled by clock B. System A should send data to system B on activation by clock A. Here you can assume the system is a chip or separate blocks in a chip which are having different clocks. System B should receive each word exactly once from system A and the data must be stable at system A while system B is sampling the data.

When the new data is valid and available at system A, it sends the Req signal to system B, and system B if it is free to receive it acknowledges the Req sent by system A by sending an Ack signal back as shown in the figure. This handshaking makes sure to send and sampling the data one word at once. In summary, if we are unknown from the relationship between clock A and clock B, an interface synchronizer can be used.

## Asynchronous FIFO

A FIFO is needed when there are two different clock domains and we need to transmit the data. We must use FIFO when the fast sending data is to be delayed to match the speed of the receiver. We come across different cases let us understand one by one.

**Case 1: The frequency of block X is greater than the frequency of block Y, and there are no ideal clock cycles on both sender and receiver sides. fx > fy.**

For example, The given specifications are fx = 80MHz which is the writing frequency, fy = 50MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. Since no idle clock cycles, the burst of data will be sent and received in consecutive clock cycles.

**Solution:**

**step 1:** The total time required to write the data one at a time will be 1/fx = 1/80MHz = 12.5 nsec. and for all signals to write it takes B*12.5nsec = 120 * 12.5 nsec = 1500 nsec.

**step 2:** The total time required to read the data one at a time will be 1/fy = 1/50MHz = 20 nsec. It means system B will read a data item from the burst at 20nsec. So it can read 1500 nsec / 20 nsec = 75 number of data in the duration of 1500 nsec.

**step 3:** Since only 75 data items are read in 1500 nsec, the remaining 120 – 75 = 45 number of data must be held by the FIFO.

So the minimum FIFO Depth must be 45.

**Case 2: The frequency of block X is greater than the frequency of block Y, and there is one clock cycle delay between two successive writes and reads. fx > fy.**

For example, The given specifications are fx = 80MHz which is the writing frequency, fy = 50MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. One clock cycle delay means exactly similar to no idle clock cycles only.

It was a tricky way of questioning. Because always there will be one clock cycle delay between alternate writes and reads. So the solution is similar to the previous one and the FIFO DEPTH will be 45.

**Case 3: The frequency of block X is greater than the frequency of block Y, and there is one ideal clock cycle between two successive writes, and there are three ideal clock cycles between two successive reads. fx > fy.**

for example, The given specifications are fx = 80MHz which is the writing frequency, fy = 50MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. The difference in the given number of idle clock cycles between writes and reads.

**Solution:**

**step 1:** Since the one idle clock cycle is given between two successive writes, it means that system X is waiting for one clock cycle after writing one data item. So overall, it takes two clock cycles to send on data. Therefore we can calculate the total time required to write one data as 2 * (1/fx) = 2 * (1/80MHz) = 25 nsec. then to write a burst of data it will take 120 * 25 nsec = 3000 nsec duration.

**step 2:** Since three idle clock cycles are given between two successive reads, it means that the system Y is waiting for three clock cycles after reading one data item. So overall, it takes four clock cycles to read one data item. Therefore we can calculate the total time required to read one data as 4 * (1/fy) = 4 * (1/50MHz) = 80ns. So in the duration of 3000 nsec, it reads 3000 nsec / 80 nsec = 37.5 ~ 37 number of data items only.

**step 3:** Since only 37 data items are read in the duration of 3000 nsec, the remaining 120 – 37 = 83 data items must be held by the FIFO.

So the minimum FIFO Depth must be 83.

**Note:** They may give the duty cycles instead of the idle clock cycles. for example for the above example if they give a duty cycle of the write enable signal is 1/2 or 50% and the duty cycle of the read enable signal is 1/4 or 25%. It is the same as the above example.

**Case 4: The frequency of block X is lesser than the frequency of block Y, and there are no ideal clock cycles on both sender and receiver sides. fx < fy.**

for example, The given specifications are fx = 30MHz which is the writing frequency, fy = 50MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. Since no idle clock cycles, the burst of data will be sent and received in consecutive clock cycles.

**Solution:**

Since the reading is faster than the writing, there is a FIFO depth of one will be sufficient.

**Case 5: The frequency of block X is lesser than the frequency of block Y, and there is one ideal clock cycle between two successive writes, and there are three ideal clock cycles between two successive reads. fx < fy.**

for example, The given specifications are fx = 30MHz which is the writing frequency, fy = 50MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. The difference in the given number of idle clock cycles between writes and reads is 1 and 3 respectively.

**Solution:**

**step 1:** Write Time for one data item = 2 * (1/fx) = 2 * (1/30) = 66.667 nsec, Write Time for burst data = 120 * 66.667 nsec = 8000 nsec.

**step 2:** Read Time for one data item = 4 * (1/fy) = 4 * (1/50) = 80 nsec. So in the duration of 8000 nsec, it will read 8000nsec/80nsec = 100 data items.

**step 3:** The remaining number of data items 120 – 100 = 20 needs to be held by the FIFO.

So, the minimum FIFO depth must be 20.

**Case 6: The frequency of block X is equaled to the frequency of block Y, and there are no ideal clock cycles on both sender and receiver sides. fx = fy.**

for example, The given specifications are fx = 30MHz which is the writing frequency, fy = 30MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. Since no idle clock cycles, the burst of data will be sent and received in consecutive clock cycles.

**Solution:**

Since both frequencies of clock domains are equal, if there is no phase difference in the clock domains we don’t need any FIFO at all, but if the phase difference is there a FIFO depth of 1 will be sufficient.

**Case 7: The frequency of block X is equaled to the frequency of block Y, and there is one ideal clock cycle between two successive writes, and there are three ideal clock cycles between two successive reads. fx = fy.**

For example, The given specifications are fx = 50MHz which is the writing frequency, fy = 50MHz which is the reading frequency. The number of data items to be transferred are 120 which is the Burst length. The difference in the given number of idle clock cycles between writes and reads is 1 and 3 respectively.

**Solution:**

**step 1:** Write time per data = 2*(1/50MHz) = 40 nsec. and Write time for a burst of data 120 * 40 nsec = 4800 nsec.

**step 2:** Read time per data = 4*(1/50MHz) = 80nsec. So for the duration of 4800nsec, it will read 4800nsec/80nsec = 60 number of data items.

**step 3:** The remaining 120-60=60 data items are to be held by the FIFO.

So, the minimum FIFO depth here must be 60.

**Case 8: A typical example of problem 1**

If the frequency of writing data is 80data per 100clock cycles and has randomization of 20 data items. The frequency of the reading data is 8data per 10clock cycles. and The given burst size is 160.

**Solution:**

**step 1:** In the worst-case let us assume the write operation completes in just 160 clock cycles(since burst size is 160, the first 80 data at 80 clock cycles and the next 80 data at the next 80 clock cycles).

**step 2:** The read time for 8 data is 10 clock cycles, and the read time for 160 clock cycles will be 160*8/10 = 128 clock cycles.

**step 3:** So the remaining data 160 – 128 = 32 must be held at FIFO.

So, here the minimum FIFO depth should be 32.

**Case 9: A typical example of problem 2**

This same question was asked to my friend in the Qualcomm interview. The problem statement or the way of giving specifications may vary but understanding the concept of FIFO depth clearly is important. Let’s see this one.

They have given some FIFO rules such that the Frequency of clock X is equaled to 1/4th the frequency of clock B. And the clock period of enable signal Y(en_y) is equaled to 100 times the clock period of the enable signal X(en_X)(HINT: Burst size is 100). The Duty cycle enables signal Y(en_B) to be given as 25%.To not underflow or overflow calculate what must be the FIFO depth.

Solution:

**step 1:** Let us assume the clock frequency of system Y is 100MHz. then according to the statement, the frequency of system X must be 100MHz/4 = 25MHz.

**step 2:** Write time per data = 1/25MHz = 40nsec. Write time for a burst of data 100*40nsec = 4000nsec.

**step 3:** The duty cycle of en_y is 25% so that it will read only for 1000nsec.

**step 4:** The remaining data of 3000nsec duration must be held by the FIFO.

So, the minimum FIFO depth will be 3000nsec/40nsec = 75.

Solve as many as the number of FIFO depth problems to clear the concept. Most of the semiconductor companies such as Analog Devices, Western Digital, and Nvidia, etc. which take a written-based test, will ask one FIFO depth question.