**Verilog** always block **(blocking** and **non-blocking** assignments) is explained in detail with examples. Also generation of MUX and Decoders Verilog.

In any digital interview, Verilog questions will be asked. Simple questions to confuse and tricky questions will be asked by an interviewer. He will be interested in knowing whether you are very clear with basic concepts or not. Verilog is a hardware description language that makes it necessary to be learned by a digital design aspirant.

Questions on blocking and non-blocking assignments, Verilog tasks vs Verilog functions, and Verilog modeling questions based on synthesis are the key concept-oriented ones that are preferred to ask by the interview panel.

Well, let us cover some of the important concepts in **Verilog HDL.**

Table of Contents

## Verilog always block and assignments

Some important points about always constructing,

1. A **Verilog always** construct starts at 0-time units and executes indefinitely or never stops, unlike an initial construct that starts at the 0-time unit and executes only once.

2. An example where always can be used is to generate a clock of a particular time period indefinitely. i.e. if T time period required is 10-time units then

always

#5 clock = ~ clock;

3. It is possible to have more than one always blocks in a Verilog module and all of them start at 0-time units and executes concurrently.

4. It is always a must to have a reg variable at LHS and RHS can be net or reg inside an always construct.

Let us consider some of the different scenarios and see how this always construct behaves,

**Situation 1, what happens for the below Verilog code snippet?**

**always @ (posedge clock)**

**y = x;**

**always @ (posedge clock)**

**x = y;**

Points to be observed are,

1. Two always blocks with the same positive edge event-triggered clock is given.

2. Verilog blocking assignment is used in both cases of the above scenario.

3. Trying to swap x and y.

Behavior would be, the above situation leads to Race Condition since always blocks execute concurrently either of the above two expressions executes depending on the simulator.

**Situation 2, what happens for the below Verilog code snippet?**

**always @ (posedge clock)**

**y <= x;**

**always @ (posedge clock)**

**x <= y;**

Points observed are,

1. Two always blocks with the same positive edge event-triggered clock is given.

2. Verilog non-blocking assignment is used in both cases of the above scenario.

3. Trying to swap x and y.

Well, this helps to swap x and y correctly. The reason is RHS of the above expressions are read first and their value is assigned to LHS once the event positive edge of the clock occurs.

We saw that Verilog non-blocking assignments helped to swap correctly. Because of this Digital design engineers always prefer to use non-blocking assignments in sequential digital circuits.

This helps to have the statements in any order and also the chances of occurrence of errors is less when non-blocking Verilog assignments are used.

**Situation 3, what happens for the below Verilog code snippet, and what are the values of z and m just before the second positive edge of the clock?**

**Given the values at time t = 0, x = 10, y = 5, z = 6 and n = 4.**

**always @ (posedge clock)**

**z <= x + y;**

**always @ (negedge clock)**

**m <= z – n;**

Points observed are,

1. Two always blocks with a positive edge event triggered clock and negative edge event triggered clock is given.

2. Verilog non-blocking assignment is used in both cases of above scenario.

Since non-blocking is used, the evaluation of RHS expressions happens at the start of the event trigger of always block with the initial values.

So, x + y = 10 + 5 = 15 is done and wait for the event to happen and do assign 15 to z. Once the first positive edge comes value is assigned to z.

Here, both always blocks started concurrently but second always block had to wait till negedge of the clock to come. So, second, always block uses the evaluated value of z instead of the initial z value.

Therefore z = 15 and m = 11 will be the right values at the start of the second positive edge of the clock.

**Situation 4, what happens for the below Verilog code snippet, and what are the values of z and m just before the second positive edge of the clock?**

**Given the values at time t = 0, x = 10, y = 5, z = 6 and n = 4.**

**always @ (posedge clock)**

**z <= x + y;**

**always @ (posedge clock)**

**m <= z – n;**

1. Two always blocks with a same positive edge event triggered clock is given.

2. Verilog non-blocking assignment is used in both cases of above scenario.

In this case, the values of z and m would be 15 and 2 respectively.

**Draw the logic circuits for below Verilog code snippets.**

**Question 1.**

**always @ (posedge clock)**

**begin**

**q1=m;**

**q2=q1;**

**end**

**Question 2.**

**always @ (posedge clock)**

**begin**

**q2=q1;**

**q1=m;**

**end**

**Question 3.**

**always @ (posedge clock)**

**begin**

**q1 <= m;**

**q2 <= q1;**

**end**

**Question 4.**

**always @ (posedge clock)**

**q2 <= q1;**

**always @ (posedge clock)**

**q1 <= m;**

**end**

## Equality in Verilog == and ===

In Verilog HDL symbol = (for assignment), == (for checking equality) and === (for exact equality match) will be used.

**for example,**

if m = 101x and n = 1010 they are matched if == operator and not for ===

if m = 101x and n = 101x they are matched if the operator is ===.

The main difference here is that == operator assumes 0 or x and 1 or x as matched, where as === not.

## Generation of a MUX

**Case 1**

In a Verilog assignment, whenever there is a nonconstant or variable in the RHS (right-hand side) of the expression it leads to the generation of **MUX.**

for example,

assign exp_out = in_data[i]; where i is a variable in RHS. leads to the generation of MUX

assign exp_out = in_data[2]; where 2 is a constant in RHS, does not lead to a generation of MUX.

**Case 2**

A Verilog conditional operator always generates a MUX in the synthesis.

for example,

assign out = select ? in_a : in_b

## Generation of a Decoder

In a Verilog HDL assignment, a non-constant or a variable in the LHS (left-hand side) of the expression, leads to the generation of a **Decoder.**

for example,

assign exp_out[select] = in_data; here, select is a variable in the LHS leads to the generation of a decoder.