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Power Calculation and Planning in Physical Design of a VLSI chip

Power Calculation and Planning in Physical Design of a VLSI chip

Power calculation and planning before any signal routing in the VLSI chip physical design is very important. As Power supply rails carry large transient currents which may distort the signal lines using electrostatic discharge if design rules are not met correctly.

Introduction to power planning

A VLSI chip in the semiconductor industry is intended to perform a specific operation and has to communicate with the outside world through various signals. To have this signal flow to the chip and out of the chip we need a power supply. Hence proper power planning became an essential part of the planning process in the back-end of the VLSI chip design.

An appropriate power supply network must be constructed by considering many aspects such as design methodologies and considerations and the process technology used.

Let us consider an example to estimate the total VLSI Chip power, what are the things the designer should plan for?. The first thing the designer can make use of low Vth (threshold voltage) devices and dynamic CMOS circuits for the design. Second thing designed should make use of low power clock gating techniques and the Third, avoid the switching noise by placing decoupling capacitors.

Key points to be considered during power planning

Generally, the power planning process is an iterative process that includes,

1. One must simulate that the higher power dissipation components in the design in the early power planning process.

2. The total VLSI chip power must be quantified at the early stage.

3. The total power of the chip and the total maximum power density of the chip must be analyzed.

4. Power fluctuations of the VLSI chip must be thought and analyzed.

5. The clock gating process will include inherent and add fluctuations to chip power, those must be taken care of.

Also Maximum, Minimum and Averaged power distribution analysis and Multicycle power fluctuations should be considered.

Power Supply I/O Pads of a VLSI Chip

Bumps and power supply I/O pads can deliver 100’s and 10’s of milliamperes of supply current which is more magnitude of the current. For example, an intel 4 Pentium processor uses a total of 423 bumps out of which around 223 bumps are used for power supply delivery to VDD and VSS or GND.

As these VDD and GND supply nets help to connect every cell in the design and provide a power source to all of them, these supply nets must be routed very first than any other signals. For proper power distribution around the entire VLSI chip, these supply nets are routed mainly in two ways.

Power planning in VLSI chip

core limited die, where the supply nets will be surrounding the core with one ring for VDD supply and one for GND power supply.

next second method, A pad limited die or I/O cell power managing, where the supply nets or power rings will be formed for the I/O cells, power trunks for core and power pad connection.

Some IC’s use both of these methods which might be having a square die, but the aspect ratio will be different compared to the above two types.

For the positive power supply, VDD special kind of power pads are used and for the negative supply, VSS or ground supply GND power rails or power buses are used.

These pads are also called dirty pads as they carry a large amount of transient current and we want to keep the signal I/O pads away from them to avoid problems such as electrostatic discharges.

What is LEF (Library Exchange Format) file

It is an ASIC2 format to represent the physical design layout of a VLSI chip. A LEF file includes the design rules to be followed for cells and their abstraction. A complete physical layout would also include DEF that is a design exchange format along with the LEF.

The different parameters included in LEF such as Layer information, the process technology, via definitions and metal widths and capacitance, and also design rules specific to the process technology.

Process technology is decided based on the descriptions defined by layer and via statements.

Here a layer can represent a cut/contact, active polysilicon, and also can be routing. A typical definition of a layer LAYER then <layername>, TYPE CUT of the layer and its SPACING and END layer.

And Via vis definition would include Via followed with <vianame> and cell name, resistance value and the layer on which via to be, the END of the via.

A typical LEF file example,

Metal Name = M8

Current Strength of M8 for 1u width = 10mA

Spacing for M8 = 25 u

Core width = 1mm

Core Height = 1mm etc..

Standard cells, Spare cell, Endcap cells, and Tie cells

What are Standard cells?

These are already predesigned and well pre-tested cells which are made available in the standard cell library to make use of them across many designs. By using these standard cells, the back-end designer saves a lot of time and cost. A designer can focus more on the product design requirements to be met using these standard cells.

The examples of standard cells would be predesigned logic cells such as AND gate, NOR gate, MUX gate, NAND gate, etc.

What are Tie cells?

Without changing the functionality of the logic circuit the floating inputs are being connected to either positive power supply VDD or ground GND through Tie cells.

What are Spare cells?

Later after the completion of the entire design (after tape out), we may require some of the cells to include to have some logic or some element of testing.

At that time it is difficult to fit the cell onto the already completed design.
It is an idea to leave some spare cells in the design, by having an assumption of we may require them for future use. An example case is whenever there is some functional engineering change order (ECO).

Spare cells will be floating on a VLSI Chip and these are predesigned and pretested standard cells.

What are End cap cells?

Each cell row-end will be placed by these king of END CAP cells which will handle the row end and tie off requirements of the end of the row. These end cap cells ensure there is no gap between the IMPLANT and WELL layers also cover power and ground rails for some areas. In this kind the helps to get rid of design rule violations.

Power Calculation with an example.

For the proper power planning, the estimated power requirements for a VLSI chip is 100mV and the supply voltage is 1 volt. A power ring is of width 2.5 microns. Also, assume there are four sets of supply nets VDD and VSS pads available around the chip. given M8 – 1u width – 10mA current-carrying strength and A square floorplan of width and height equals 1mm. Metal spacing is 25 microns.

Since the power P and voltage V are given, we can calculate the current I using the formula P=VI.
Modifying the formula for current i.e. I = P/V implies I = 100mW/1v = 100mA.
Here comes the total current estimated I is 100 milliamperes.

Since there are four VDD pads, then each pad will consume 100mA/4 = 25mA of current.

A 1u width M8 metal element is carrying a current of 10mA and therefore for a 2.5u width of M8 element power ring will carry a current of 2.5mA.

Now we need to calculate the number of vertical stripes and the width of the stripes required.

The number of stripes would be the ratio of core width to the spacing between the metals.
hence the number of stripes = 1mm/25u = 40 number of vertical stripes.

The width of these vertical stripes can be calculated by the formula is the ratio of the width of the power ring upon the total number of vertical stripes. which is 2.5u / 40 = 0.625 micron.

The number of horizontal stripes and width of the stripes required is

The number of stripes would be the ratio of core height to the spacing between the metals.
hence the number of stripes = 1mm/25u = 40 number of horizontal stripes.

The width of these horizontal stripes can be calculated by the formula is the ratio of the width of the power ring upon the total number of horizontal stripes. which is 2.5u / 40 = 0.625 micron.

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