The Digital Texas Instruments Interview Questions are completely memory-based. Refer to these given questions and prepare accordingly. Please keep in mind that these are not the exact question that may come in the Interview test and the values given in the questions may also differ.

1. **Ripple counter** shown below works as (assume the **preset** is the **asynchronous** and **initial state is 0** for all three flip-flops).

**Options**

1. Mod 5 Down counter

2. Mod 3 Up counter

3. Mod 3 Down counter

4. Mod 5 Up counter

2. An **AND gate** drives a **load** whose capacitance is much **higher** than the **parasitic capacitance of the transistor** inside the AND gate. **Signal A is a 200 MHz clock**. **Signal B is a 400 MHz clock** whose edges are offset from the edges of the **200 MHz clock.**

When both the inputs of the **AND** gate are tied to A, then the **power dissipation** is equal to **P**. When the inputs of the **AND** gate are connected to A and B respectively, the power dissipation is **equaled** to what?

**Options**

1. P/2

2. 2P

3. P

4. 0

3. **Statement 1:** Area wise both implementations are the same. **Statement 2:** Critical path is longer in 2 compared to 1

**Options**

1. 1 is false, 2 is true

2. 1 is true, 2 is false

3. Both 1 and 2 are true however depending upon input arrival time we may choose either of the circuits

4. If D is a static signal circuit two will take lesser power compared to circuit 1.

4. How many **2:1 multiplexers** are needed to implement a **3-input NAND gate**?

**Options**

1. 4

2. 3

3. 2

4. 5

5. **INV1, INV2,** and **INV3** are similar **inverters. INV1** gives a **delay** of 1ns when driving a capacitance **C = 0.1 pF.** The **rise** and **fall delays** are **equal.** IN and INZ are complementary signals.

What is the delay of **INV2** if **C1 = 0.2 pF**?

**Options**

1. 2 ns

2. 1 ns

3. 5 ns

4. 4 ns

6. **IIR filter** with equation **y(n) = a*x(n)+(1-a)*y(n-1) [0<a<1]** is implemented for **a = 0.875** in **16 bit microprocessors**. How many **previous** outputs contribute to the **present** output?

**Options**

1. Infinite

2. 5

3. 6

4. 7

7. **Optimize** the following logic using **K-map**. Input is assumed to be a **5-bit binary number** (**ABCDE** and A is MSB)

**Options**

1. CE, C’E’

2. K-map can not be used if there are more than 4 variables

3. CEA’, C’E’A’, CDA, and CEA

4. CE, B’C’E’, and C’D’E’

8. **SRAM** cell is given below.

**Write operation:** bit and bit’ are forced and the word line is made **high.**

**Read operation:** bit and bit’ are pre-charged to **VDD** and the word line is made **high.**

If there is large **resistance** in the **pass gate** path.

**Options**

1. No difference at all

2. Write will become tougher

3. There is a high potential for reading failure

4. Write will become easier

9. The **LED (Light-Emitting Diode)**

**Options**

1. Emits light when both S1 and S2 are closed

2. Emits light when both S1 and S2 are open

3. Emits light when only S1 or S2 is closed

4. It does not emit light irrespective of the switch position.

10. Three Capacitors **C, 2C, and 3C** are **pre-charged** to voltages of **0V,1V, and 1V** respectively. What is the **voltage at V0** once they are **stacked** as shown in the figure below?

**Options**

1. 1.5V

2. 2V

3. 0.33V

4. 1.75V

11. In the circuit shown below, **switch S1** is an identical switch that is **turned ON and OFF periodically.** That is **ON** for **40 percent** of the time and **OFF for 60** percent of the time. What is the **average** value of **VOUT? if R’ = 3*R, V1 = 10V, V2 = 6V.**

**Options**

1. 6.4V

2. 7V

3. 4V

4. 7.6V

12. The **transistor-level** circuits of gates are shown below in the figure.

**Gate 1** is required to drive the **load capacitance** of **C1** and **Gate 2** is required to drive a **load capacitance** of **C2**. The self **parasitic** capacitance of the transistor can be rejected. The **W by L ratios of the transistors** is indicated beside each transistor.

**For Gate 2**, both **inputs A and B** are **shorted.** **C1 = 1 pF and C2 = 2 pF**. If **Gate 2** has an output rise time of **100ps,** then the **output rise time **of **Gate 1** is equal to what?

**Options**

1. 500 ps

2. 150 ps

3. 250 ps

4. 300 ps

13. In a **binary fixed-point** system with **2’s complement** representation, a number format is specified to fix **WL and FL**. **Word length WL** is the total **number of bits**. **Fraction length FL** is the number of **bits used for fraction length**.

For **binary fixed point**, if the absolute value of the **smallest positive number is X** and the absolute value of the **smallest negative number is Y** then,

**Options**

1. X and Y are the same if signed and (WL-1) == (2 * FL)

2. X and Y are always the same.

3. X and Y are always different.

4. X and Y are the same if signed and (WL-FL)<(FL+1)

14. **D1** to **D2** are devices that communicate with each other via the **BUS.**

**Statement 1:** Architecture 1 allows simultaneous communication between two separate pairs of devices.

**Statement 2:** In architecture 1 **D2 and/or D5** need to be used even when they are not transmitting or receiving data.

**Statement 3:** Architecture 2 allows simultaneous communication between two separate pairs of devices.

**Options**

1. Only 1 is true

2. Only 3 is true

3. Only 2 is true

4. 1 and 2 are true

15. The **diode** has a **forward drop** of **0.7 Volts** when it is made **ON.** The below circuit is **operating** in **steady-state** with **Vo** initially at a very **high positive voltage** such that the **diode is OFF**.

Gradually the voltage at **Vo** is **reduced.** When will the diode **conduct?** When **Vo** is

Options

1. 0.3V

2. -0.7V

3. -1.7V

4. The diode can never conduct.

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Happy Reading, All the best.