FSM-Finite State Machine-Questions-Answers | DIGIQ Digital Interview by VLSI Universe - April 30, 2020July 21, 20210 The Sequential FSM Finite State Machine DIGIQ based questions are very important for any digital interview. Sharing a few of the FSM questions with answers. The question sequence or pattern detector will be a fixed question in many written tests such as NVIDIA, Western Digital, Analog Devices, etc. FSM Finite State Machine Questions and Answers 1. Design a finite state machine FSM for a serial two's complement block and also draw the logic diagram associated with it by using D-flipflop. Answer: The main logic behind this is, start from the least significant bit and retain the bits until and first 1-bit has occurred. Once a 1-bit is found, start complementing the bits if 1 makes it 0 and if 0 make it 1. Note
MediaTek interview questions and experience Analog Digital Interview Interview Questions by VLSI Universe - April 29, 2020July 21, 20210 Here are some MediaTek interview questions and experiences which had been will be shared. Refer to these interview questions and experience words prepare accordingly. As we all know MediaTek is a fabless semiconductor hardware company. The company provides or produces the processor IC chips for wireless communication. Most of the time the company hires communication stream aspirants, but it also prefers VLSI specialization aspirants as it works on semiconductor hardware physical design. The company MediaTek conducted the test through cocubes online exam. The online test included around 49 objective questions and was given a time limit of 65 minutes. Solving the online test very fast was a must need. The online test had a total of four sections which are Aptitude (Ten questions) C (Ten
Synopsys VLSI Interview Questions – 2020 Analog Digital Interview Interview Questions by VLSI Universe - April 28, 2020July 21, 20210 The placement experience with Synopsys and the questions asked in the Synopsys VLSI interview are listed. The interview happened on the college campus of NIT (National Institute of Technology). The interview process had a written test followed by the interview round. Synopsys written test: The written test was conducted for a duration of 120 minutes which had a total of 65 questions. The written test included four sections in which there were 10 aptitude questions which were easy levels. And a section of Digital Electronics questions which consisted of a total of 25 questions. An Analog section with 20 questions 20 marks and of course there was a programming section that had C, C++, and Verilog programming questions a total of 10 questions with 10
FIFO Depth Calculation VLSI Digital Interview by VLSI Universe - April 23, 2020July 21, 20210 The FIFO depth calculation made easy(use synchronizers) is the most asked question in the interviews and a very important topic any VLSI or Electronics engineer must know. When we want to establish a connection between two different asynchronous clock blocks a common option is to use synchronizers. Here the term asynchronous clock domain refers to the blocks of circuits which do not share a common single clock. Let us understand how the connection can be established between them. Table Of Contents Synchronizers FIFO case1 fx > fy, no idle clocks case2 fx > fy, one idle clock case3 fx > fy, one and three idle clocks case4 fx < fy, no idle clocks case5 fx < fy, one and three idle clocks
