The Maxlinear is an American-based semiconductor hardware company. The interview experience and the questions asked in the interview will be shared in this article.

The interview was conducted for the Digital Design Engineer profile. The number of questions which will be listed below may vary in terms of the parameter values but the question statement structure will be the same.

Try to refer to these questions and excel in your preparation level for the interview.

Max linear Interview process:

The interview test (which was a written test) was for a total of 90 minutes.

The interview written test had two separate parts.

The first one was the objective section which consisted of around 5 to 6 questions and each question had a weightage of 2 marks each.

The second section was the Technical section which was totally descriptive. It consisted of around 12 questions that carry a weightage of 5 marks each. So, this section was for a total of 60 marks.

Max linear Objective interview questions:

Which of the CMOS logic gate is faster?

NAND logic gate or AND logic gate?

What is the total power dissipation of a CMOS logic circuit for given capacitance C and the frequency of operation F?

A circuit was given which contained an NMOS transistor and a PMOS transistor. And asked to calculate the drain voltages at their drain terminals.

What are the total numbers of multipliers needed to design a complex multiplier?

Max linear Descriptive interview questions:

Design a circuit such that whenever an enable is ON, the input data should be complemented. Or else, the input data should be added to the output without any change.

If the radius of a circle is given as 4 centimeters and the distance between points Q and R is 7 centimeters, Then what is the value of OX.(X is a projection of P on QR).

Design a Time Division Multiplexing (TDM) system which has a data rate of 120 Mbps with three different streams. And the TDM system should work on any possible combinations of X, Y, and Z which satisfy the equation 10X+40Y+80Z=120 Where X, Y, and Z are a number of streams of 10 Mbps, 40 Mbps, and 80 Mbps respectively.

Design a circuit such that it takes random bits 1,0 such as reset the counter if it sees the sequence “10110”, Increment the counter if it sees the sequence “10101”, and Decrement the counter if the sequence is “01101”.

Design a combinational circuit such that when the car is stopped or turned OFF, the headlight should turn off after 5 seconds if the car is ON and Given system clock frequency F is given as 1 MHz.

Find the maximum clock frequency for the given circuit below. The clock to q delay (Tcq) is not given.

Design a circuit such that it should unlock a safe if it sees a sequence “1011”(some 4-bit sequence). If the sequence is wrong three times, an alarm should be sounded. sequence detector.

Given the FIR filter and h0 = h4 and h1 = h2. Implement the FIR filter by using the minimum number of multipliers.

Implement the given equation Y = a+b+c+d+e+f (all of them have same number of bits). Given the clock of frequency 300 MHz and an n-bit adder which gives a delay of n nanoseconds. Implement the circuit such that no timing violation occurs. Using as many as the number of adders and registers is allowed.

For the above implementation what are all changes required to get Z = G * Y.

Design a 1 line code for identifying whether a given number is the power of 2 or not.

One question on Elmore’s delay was there in that there was a branch out. It was of the multi-stage network.