The FIFO depth calculation made easy(use synchronizers) is the most asked question in the interviews and a very important topic any VLSI or Electronics engineer must know. When we want to establish a connection between two different asynchronous clock blocks a common option is to use synchronizers. Here the term asynchronous clock domain refers to the blocks of circuits which do not share a common single clock. Let us understand how the connection can be established between them. Table Of Contents Synchronizers FIFO case1 fx > fy, no idle clocks case2 fx > fy, one idle clock case3 fx > fy, one and three idle clocks case4 fx < fy, no idle clocks case5 fx < fy, one and three idle clocks