The circuit pitfalls such as Back gate coupling, Threshold power drops, Hot spot, and supply noise are explained. Ignoring these may cause chips to fail. Back gate coupling The dynamic logic gates driving multiple i/p static CMOS logic gates are susceptible to the back gate coupling effect. As an example, a dynamic NAND gate driving a static NAND gate is shown in the figure below. The gate to source capacitance (Cgs1) of the N1 transistor. Let us assume the dynamic NAND logic gate is in evaluation mode and output at node X is floating High. The input of the static NAND logic gate B is initially Low. So the output Y is High. And the internal node W is charged up to VDD