The stack effect is often advantageous (reduces DIBL effect) and whereas Charge sharing is a problem to us (very critical in dynamic and semi-dynamic circuits). Stacking effect in CMOS The leakage through two series OFF transistors is much lower than that of a single transistor because of the Stack effect. The below figure (a) shows two series OFF transistors with their Gate terminals at ZERO volts. The drain of N2 is at VDD, so that the stack will leak because of DIBL (Drain induced barrier lowering), However, the middle node Vx settles to a point that each transistor has the same current. If Vx is small, N1 will see a much smaller DIBL effect and it will leak less. As Vx rises, DIBL (Gate to source)