DIBL GIDL BTBT and Tunneling effect in CMOS Devices CMOS by VLSI Universe - May 5, 2020July 21, 20210 One must consider these DIBL, GIDL, BTBT, and Tunneling effects while designing in CMOS because these may cause serious issues on the functionality of the design. Understanding these terms is very important in the VLSI design. The PN junctions between diffusion-substrate or diffusion-well will form diodes and also well-substrate junction will be another diode. Because of that, only the substrate and well terminals are connected to the ground or to the supply voltage in PMOS to ensure these diodes will remain to reverse biased but however, these reverse biased diodes will conduct a small amount of current Td and leads to junction leakage. Drain Induced Barrier Lowering (DIBL) DIBL(Drain Induced Barrier Lowering) in MOSFETs leads to a reduction of the Vth of transistors
Dynamic Power dissipation in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The CMOS dynamic power is the power dissipated when the logic gate is in the active state. It is mainly due to the switching activity of the i/p signal or mainly due to the charging and discharging of internal node capacitances. Pdynamic = ∝ * CL * (Vdd)^2 * f The CMOS dynamic power (Pdynamic) dissipation is mainly due to The charging and discharging of the load capacitances as the gate switches from one logic to another logic. The short circuit current or leakage current while both PMOS and NMOS stacks are partially ON when not necessary. Activity Factor (∝) The clock gating techniques It will disable the clock to the IDLE portions of the design and hence reducing the power dissipation because of the
Latchup and its prevention in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 Latchup is the most common problem in the CMOS transistor. Mainly causes due to the formation of BJTs (PNP and NPN) and can be prevented using Guard Rings. First of all, this is the most important VLSI interview question. Most of the interview guys prefer to ask this question to check the basics of the candidate regarding MOS and its second-order effects. You must also read these topics which I am listing below. 1. Non-ideal characteristics of MOSFET such as Velocity Saturation, Mobility degradation, Channel length modulation (CLM), body effect, subthreshold conduction, DIBL (Drain induced barrier lowering), BTBT (Band to band tunneling), GIDL (Gate induced barrier lowering), 2. the Tunneling effect, 3. Latchup, 4. Stack effect, 5. Charge sharing effect, 6. Short channel effects, and Narrow channel effects. Latchup: Latchup
Threshold Voltage | VTCMOS | Body bias CMOS by VLSI Universe - April 21, 2020July 20, 20210 The main role of VTCMOS, threshold voltage of CMOS, body bias method in the static power reduction techniques is explained. The main role of the body bias method in the static power reduction techniques The threshold voltage Vth can be defined as the gate voltage Vg when the inversion with a density similar to that of the concentration of substrate starts at an oxide SiO2 interface in a CMOS device. When the gate voltage Vg is not enough to reach threshold voltage Vth, the width W of the depletion region under the gate is a function of the gate voltage Vg. Threshold voltage dependence on substrate doping density 1. The threshold voltage Vth is less sensitive to the doping density of the substrate when the
CMOS Inverter | VTC | Noise Margin June 2021 CMOS by VLSI Universe - April 21, 2020July 20, 20210 One of the main advantages of the CMOS inverter is it consumes power only during the transients/operation. At the steady-state, it consumes no power. The difference between hole mobility and electron mobility can be compensated and make tphl and tplh, rise, and fall delays more compatible by designing or adjusting the width by length W/L ratios of the PMOS and NMOS devices. The symmetric tphl and tplh, rise and fall delays facilitate the very easy circuit design. In CMOS inverter the input-output I/O transfer curve can be symmetric wrt. (with respect to) the center of the signal swing so that the NM noise margin can be optimized here. The load capacitance CL can be reduced by scaling. And by increasing the width by
