Stack effect and Charge sharing problem in Dynamic CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The stack effect is often advantageous (reduces DIBL effect) and whereas Charge sharing is a problem to us (very critical in dynamic and semi-dynamic circuits). Stacking effect in CMOS The leakage through two series OFF transistors is much lower than that of a single transistor because of the Stack effect. The below figure (a) shows two series OFF transistors with their Gate terminals at ZERO volts. The drain of N2 is at VDD, so that the stack will leak because of DIBL (Drain induced barrier lowering), However, the middle node Vx settles to a point that each transistor has the same current. If Vx is small, N1 will see a much smaller DIBL effect and it will leak less. As Vx rises, DIBL (Gate to source)
CMOS Inverter | VTC | Noise Margin June 2021 CMOS by VLSI Universe - April 21, 2020July 20, 20210 One of the main advantages of the CMOS inverter is it consumes power only during the transients/operation. At the steady-state, it consumes no power. The difference between hole mobility and electron mobility can be compensated and make tphl and tplh, rise, and fall delays more compatible by designing or adjusting the width by length W/L ratios of the PMOS and NMOS devices. The symmetric tphl and tplh, rise and fall delays facilitate the very easy circuit design. In CMOS inverter the input-output I/O transfer curve can be symmetric wrt. (with respect to) the center of the signal swing so that the NM noise margin can be optimized here. The load capacitance CL can be reduced by scaling. And by increasing the width by
