One must consider these DIBL, GIDL, BTBT, and Tunneling effects while designing in CMOS because these may cause serious issues on the functionality of the design. Understanding these terms is very important in the VLSI design. The PN junctions between diffusion-substrate or diffusion-well will form diodes and also well-substrate junction will be another diode. Because of that, only the substrate and well terminals are connected to the ground or to the supply voltage in PMOS to ensure these diodes will remain to reverse biased but however, these reverse biased diodes will conduct a small amount of current Td and leads to junction leakage. Drain Induced Barrier Lowering (DIBL) DIBL(Drain Induced Barrier Lowering) in MOSFETs leads to a reduction of the Vth of transistors