Designing a circuit with great speed or to meet the delay constraints, we need to find the fastest logic function. The optimized implementation of a logic function with great speed is a key task. The method of logical effort is the easiest way to calculate the delay in the MOS circuit. This method specifies the proper number of various logic stages on a path and the appropriate size of the transistor for the gates. Let us see how we can calculate the delay of the circuit and what are parameters we need to know. 1. The delay in a logic gate (d) The delay in a logic gate is mainly due to two components. The parasitic delay (p) and the stage effort/effort delay