Backgate coupling | Threshold power drops | Hot spots | Supply noise CMOS by VLSI Universe - May 5, 2020July 21, 20210 The circuit pitfalls such as Back gate coupling, Threshold power drops, Hot spot, and supply noise are explained. Ignoring these may cause chips to fail. Back gate coupling The dynamic logic gates driving multiple i/p static CMOS logic gates are susceptible to the back gate coupling effect. As an example, a dynamic NAND gate driving a static NAND gate is shown in the figure below. The gate to source capacitance (Cgs1) of the N1 transistor. Let us assume the dynamic NAND logic gate is in evaluation mode and output at node X is floating High. The input of the static NAND logic gate B is initially Low. So the output Y is High. And the internal node W is charged up to VDD
Dynamic Power dissipation in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The CMOS dynamic power is the power dissipated when the logic gate is in the active state. It is mainly due to the switching activity of the i/p signal or mainly due to the charging and discharging of internal node capacitances. Pdynamic = ∝ * CL * (Vdd)^2 * f The CMOS dynamic power (Pdynamic) dissipation is mainly due to The charging and discharging of the load capacitances as the gate switches from one logic to another logic. The short circuit current or leakage current while both PMOS and NMOS stacks are partially ON when not necessary. Activity Factor (∝) The clock gating techniques It will disable the clock to the IDLE portions of the design and hence reducing the power dissipation because of the
