Transistor sizing W/L | CMOS | VLSI CMOS by VLSI Universe - April 23, 2020July 21, 20210 The sizing of the transistor can be done using RC delay approximation. The RC Delay Model helps in delay estimation CMOS circuit. The RC delay model treats the non-linear transistor current-voltage I-V and capacitor voltage C-V characteristics with their equivalent resistance and capacitance model. This RC delay model approximates a transistor as a switch with a series of resistance or effective resistance R (Which is the ratio of the average value of Vds to Ids). The size of a unit transistor is approximated as 4/2 lambda. The RC circuit equivalent models for the PMOS and NMOS transistors are shown below. Here the k width of both PMOS and NMOS transistors is contacted to Source S and drain D. Since the holes in PMOS have lower mobility compared to electrons in the NMOS transistors, the PMOS will have twice the resistance of the NMOS. The n-well is usually tied with the High voltage because the capacitors of PMOS are shown with the VDD as their second terminal in the figure shown above. Similarly in nMOS, the capacitors are connected to the ground because usually p-well will be connected to lower supply. 1. The NMOS transistor which is having k times of width will have the resistance of R/k. 2. Similarly, A unit PMOS transistor which is having the k times of width will have the resistance of 2R/k. This is because of PMOS transistor will have greater resistance compared to the NMOS transistor because its mobility is less. The value of R will be typically on the order of 10kOhm for a single transistor. An Example Let us understand the concept of transistor sizing with an example. Given the logic function Y = A ( B + C ) + D E and asked to size the PMOS and NMOS transistors. Solution: PMOS sizing: For a unit PMOS transistor, the effective resistance with the width k is given by 2R/k. By looking at the pull-up network in the above circuit, we should find out the worst-case or the longest path to VDD. In the above network, the path E-C-B is the longest path. So we can write the equation (2R/k)+(2R/k)+(2R/k) = R, where R is the effective resistance. The equation gives the value of k = 6. Therefore the k value transistors E, C, and B will be 6. One more path D-C-B also contributes to the worst-case or longest path, So the k value of the transistor D also becomes 6. The transistor A is equivalent to two transistors B and C (by looking at the circuit). Therefore we can write 2R/k = 2 * 2R/6 Since we know the k values of B and C transistors. Therefore the k value of transistor A is 3. NMOS sizing: For a unit NMOS transistor, the effective resistance with the width k is given by R/k. In the above network, the worst-case or the longest path can be seen is with two transistors. (The paths A-B, A-C, and D-E). So we can write the relation 2 * R/k = R, So the value of k of all the NMOS transistors will be 2 since all are in the longest path. Also, study, 1. Complete ASIC Design Flow 2. Latchup and its prevention in CMOS 3. DIBL, GIDL, BTBT, and Tunneling effect 4. Charge Sharing and Stack effect 5. Velocity Saturation, Mobility Degradation, Channel Length Modulation and Body Effect.
