The difference between latch and flipflop VLSI VLSI Design by VLSI Universe - April 23, 2020July 20, 20210 The difference or the comparison between the latch-based design and the flip-flop-based design is explained briefly. Let us compare the two types of design a Latch-based design and a Flipflop or Register-based design. These also help to understand the advantages and disadvantages of the latch and flip-flop. Latch Flip-flop 1 A Latch is a transparent device and is level-sensitive or pulse-sensitive. Either it can be a positive level triggered or negative level triggered. A flip-flop is also a transparent device, which is made up of a pair of level-sensitive latches, and the flip-flop is edge sensitive. 2 The latch is very less sensitive to the pulse duration i.e. soft barrier. The flip-flop is more sensitive to the pulse transition i.e. hard barrier. 3 The enable pin EN in the latch
Method of logical effort | Multi-stage networks CMOS by VLSI Universe - April 22, 2020July 20, 20210 Designing a circuit with great speed or to meet the delay constraints, we need to find the fastest logic function. The optimized implementation of a logic function with great speed is a key task. The method of logical effort is the easiest way to calculate the delay in the MOS circuit. This method specifies the proper number of various logic stages on a path and the appropriate size of the transistor for the gates. Let us see how we can calculate the delay of the circuit and what are parameters we need to know. 1. The delay in a logic gate (d) The delay in a logic gate is mainly due to two components. The parasitic delay (p) and the stage effort/effort delay
Qualcomm Interview Experience 2020 Interview Questions by VLSI Universe - April 22, 2020July 20, 20210 This interview experience is just to guide the students about how the process happens and how the preparation level should be. No guarantee of the questions that will appear again in the exam. Do read it and understand the process. The Written exam was conducted by hirepro. Two profiles were there Software and Hardware Engineer. You can choose between Electronics, Communication, and or Software. Each profile has three sections with each profile having 20 questions and a time limit of 30 minutes. After 30 minutes that section will be disabled. First Section: Aptitude, Second Section: C MCQ's (Multiple Choice Questions), Third Section: We can choose between any one of Electronics, Communication, or software. Qualcomm Aptitude A seller sells 200 products a month for 100 each. If
Threshold Voltage | VTCMOS | Body bias CMOS by VLSI Universe - April 21, 2020July 20, 20210 The main role of VTCMOS, threshold voltage of CMOS, body bias method in the static power reduction techniques is explained. The main role of the body bias method in the static power reduction techniques The threshold voltage Vth can be defined as the gate voltage Vg when the inversion with a density similar to that of the concentration of substrate starts at an oxide SiO2 interface in a CMOS device. When the gate voltage Vg is not enough to reach threshold voltage Vth, the width W of the depletion region under the gate is a function of the gate voltage Vg. Threshold voltage dependence on substrate doping density 1. The threshold voltage Vth is less sensitive to the doping density of the substrate when the
CMOS Inverter | VTC | Noise Margin June 2021 CMOS by VLSI Universe - April 21, 2020July 20, 20210 One of the main advantages of the CMOS inverter is it consumes power only during the transients/operation. At the steady-state, it consumes no power. The difference between hole mobility and electron mobility can be compensated and make tphl and tplh, rise, and fall delays more compatible by designing or adjusting the width by length W/L ratios of the PMOS and NMOS devices. The symmetric tphl and tplh, rise and fall delays facilitate the very easy circuit design. In CMOS inverter the input-output I/O transfer curve can be symmetric wrt. (with respect to) the center of the signal swing so that the NM noise margin can be optimized here. The load capacitance CL can be reduced by scaling. And by increasing the width by
