Memory is a very important component in the VLSI Semiconductor industry. In VLSI Circuits’ memories play a key role in storing huge data. Memory testing in VLSI using Algorithms and Patterns efficiently is important. Built-in self test, self diagnosis, redundancy analysis and self repair.

Various test algorithms which helps in testing of memories such as BIST compiler and BIST for RAM in Seconds. Memory faults and basics of checkerboard algorithm and march tests or algorithm will be discussed.

Introduction to Memory Testing

In the current situation the world is producing large amount of data which needs to stored in the memories. So memory technology is a growing technology in the semiconductor market. Understanding and improving the memory testing in VLSI is very important because they don’t have the logic circuits or any sequential elements like flops in them.

We have to have separate techniques, test strategies and methodologies for memory testing as they don’t have similar fault models and scan design techniques cannot be reused here. In short we cannot apply regular DFT techniques in the memory. Different fault models such as Stuck at fault, Stuck open fault, Transient faults, Data retention faults, Coupling faults, and Read disturb faults with their respective notations.

Basics of Memory Architecture

An architecture of a memory model constitutes of an array of memory cells. The array of memory cells are in the two-dimensional form. A full address is fed to memory through an address bus to row decoder and a column decoder. Row decoder decodes the address and enables the rows based on the address. Similarly, the Column decodes the address from the bus to enable associated column cell arrays. The further memory cell is connected to A sense amplifier, which senses the data stored in the memory cell array amplify it, and sends the data out.

As shown in the above memory model the intended data can be written into the memory or the data to be read out from the memory. The Read or Write enable signal is passed to the special circuitry to perform the memory operations.

We need to test the memory whether the correct data is being written or readout of the memory which is an important task.  Basic and Typical examples of memory are 1T DRAM and 6T SRAM. Sense amplifier plays a very crucial role and amplifying the data by considering the threshold for logic 1 and logic 0. The performance of the memory is analyzed based on how many clock cycles are required to write the data into the cell and clock cycles required to read the data out of the cell.

Fault Models in the memory cell array in Memory Testing

One needs to understand the various fault models used in the memory testing unlike fault models in the DFT of regular combinational circuits and sequential circuits(That is fault models, in this case, are differently analyzed as memories don’t have logic gates).
Before understanding the fault models we need to understand the notations

1. An up arrow ↑ denotes the rising transition during a write operation.
2. A down arrow ↓ denotes the falling transition during read operation.
3. An up/down arrow denotes either rising or falling transition.
4. Reversed A ∀ denotes any operation at the cell.
5. <S/F> denotes the operation activating the fault upon the faulty value of the memory cell.

Now let us list out the fault models in the memory testing,

SAF – Stuck at fault

Here there can be two faults, a stuck at 1 fault and a stuck at 0 fault. The notation for these can be, for stuck at 0 its < ∀/0 > which says for any operation on the cell, the cell response is 0 only. And for stuck at 1 its < ∀/1 > which says for any operation on the cell, the cell response is 0 only.

SOF – Stuck open fault

A stuck open fault occurs when there is a discontinuity in a word line or a switch got permanently open.

TF – Transient Faults

Here there can be two faults, a rising transient fault, and a falling transient fault. The notation for these can be, for rising transient fault its < ↑/0 > which says for the rising operation of the cell, the cell response is 0 only which has to 1. And for falling transient fault its < ↓/1 > which says for falling operation of the cell, the cell response is 1 only which has to be 0.

DRF – Data Retention Fault

This kind of fault model arises if a cell becomes incapable to hold the data or retain the data for a specified period of time. here the memory cell loses its data spontaneously and not because of READ or WRITE operations.

CF – Coupling faults

There are three kinds of coupling faults
1. Clin – Inversion Coupling fault, This kind of fault occurs when one cell transition leads to an inversion of other cell content.
2. CFid – Idempotent Coupling fault, This kind of fault occurs when one cell transition leads to a constant value either 1 or 0 in other cell content.
3. CFst – State Coupling Faults, — Here the coupled cell is forced to a particular value only if the coupling cell is in this state; <0;0/1>, <1;0/1>, <0;1/0>, or <1;1/0>.

RDF – Read Disturb Faults

This kind of fault occurs during read operation. If the cell value is getting continuously flipped during the read operation we say it as Read disturb fault (RDF).

TEST ALGORITHMS or PATTERNS IN Memory Testing

Test algorithms are required to do memory testing in VLSI to reduce the time complexity and to cover all the possible fault models such as SAF – Stuck at faults, CFs – Coupling faults, and AFs –  Address decoder faults.

Let us take an example summary table which shows the different sized memory being tested using different memory algorithms with their time complexities. For the below table of calculations, the patterns are applied at the rate of 100M read or write operations per second.

March Test Notations

MSCAN – Memory Scan Algorithm in Memory Testing

{⇑(w0); ⇑(r0); ⇑(w1); ⇑(r1);}

Limitations of zero-one or MSCAN algorithm.

March Test – bit-oriented March C algorithm in Memory Testing

(w0); – M0 March Element

⇑(r0w1); – M1 March Element

⇑(r1w0); – M2 March Element

⇓(r0w1); – M3 March Element

⇓(r1w0); – M4 March Element

(r0); – M5 march Element

I hope by now you were able to understand the notations, you are able to clarify the purpose of each of the above march elements.

The time complexity of the March Test algorithm is 10N, where N is the number of memory cells in the memory cell array.

Benefits of March Test Algorithm

1. The March test completely detects all the fault models such as SAF – stuck-at faults, unlinked address decoder faults AFs, and unlinked Transient faults TFs.

2. It also detects all the CFs- coupling faults such as CFin – Inversion Coupling faults, CFid – Idempotent Coupling faults, and CFst – State Coupling Faults.

3.  To detect SOFs – Stuck open faults from the memory cell memory cells M1 and M2 are to be extended as shown below,

from ⇑(r0w1); – M1 to ⇑(r0w1r1); – M1 March Element extended and

from ⇑(r1w); – M2 to ⇑(r1w0r0); – M2 March Element extended.

4. The current March C algorithm can be modified to work with word-oriented memories, as shown below

Here the idea is to replace 0 with a and 1 with a’ from the existing March C Algorithm, where a is a data word.

Faults Simulator in Memory Testing – RAMSES

Memory BIST Built-Inn Self Test) Model in Memory Testing