Backgate coupling | Threshold power drops | Hot spots | Supply noise CMOS by VLSI Universe - May 5, 2020July 21, 20210 The circuit pitfalls such as Back gate coupling, Threshold power drops, Hot spot, and supply noise are explained. Ignoring these may cause chips to fail. Back gate coupling The dynamic logic gates driving multiple i/p static CMOS logic gates are susceptible to the back gate coupling effect. As an example, a dynamic NAND gate driving a static NAND gate is shown in the figure below. The gate to source capacitance (Cgs1) of the N1 transistor. Let us assume the dynamic NAND logic gate is in evaluation mode and output at node X is floating High. The input of the static NAND logic gate B is initially Low. So the output Y is High. And the internal node W is charged up to VDD
Velocity saturation – Mobility degradation – body effect – CLM CMOS by VLSI Universe - May 5, 2020July 21, 20210 The non-ideal current-voltage effects such as velocity saturation, mobility degradation, body effect, and the channel length modulation CLM are explained. Velocity Saturation At the high lateral electric field Elat that is equal to Vds/L, the velocity of the carrier ceases to increase linearly with the field strength is called Velocity saturation. The velocity saturation results in lower Ids that which is expected at High Vds. Mobility Degradation At high vertical field strengths Evert that is equal to Vgs/tox, the carriers scatter in the oxide SiO2 interface and the process gets slower is called Mobility degradation. Mobility degradation also reduces the current Ids that are expected at high Vgs. Channel length modulation CLM The saturation current Isat of the non-ideal transistor increases with Vds, which is mainly caused by
Synchronizers and Metastability in Digital Logic Circuits CMOS Interview Questions by VLSI Universe - May 5, 2020July 21, 20210 The circuits which accept the input that can change at arbitrary times and produces output with a nonzero probability of Metastability are Synchronizers. The sequential logic elements are mainly characterized by the setup and hold times. If the input data changes before the setup time the output reflects a different new value after a bounded delay. If the input data changes after the hold time the output reflects a different old value after a bounded delay. and If the input data changes between the setup and hold time constraint or aperture then the output may be unpredictable and irrelevant. That is the output may go to a metastable state. Now let us analyze how a Latch will respond to a voltage that will change
DIBL GIDL BTBT and Tunneling effect in CMOS Devices CMOS by VLSI Universe - May 5, 2020July 21, 20210 One must consider these DIBL, GIDL, BTBT, and Tunneling effects while designing in CMOS because these may cause serious issues on the functionality of the design. Understanding these terms is very important in the VLSI design. The PN junctions between diffusion-substrate or diffusion-well will form diodes and also well-substrate junction will be another diode. Because of that, only the substrate and well terminals are connected to the ground or to the supply voltage in PMOS to ensure these diodes will remain to reverse biased but however, these reverse biased diodes will conduct a small amount of current Td and leads to junction leakage. Drain Induced Barrier Lowering (DIBL) DIBL(Drain Induced Barrier Lowering) in MOSFETs leads to a reduction of the Vth of transistors
Stack effect and Charge sharing problem in Dynamic CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The stack effect is often advantageous (reduces DIBL effect) and whereas Charge sharing is a problem to us (very critical in dynamic and semi-dynamic circuits). Stacking effect in CMOS The leakage through two series OFF transistors is much lower than that of a single transistor because of the Stack effect. The below figure (a) shows two series OFF transistors with their Gate terminals at ZERO volts. The drain of N2 is at VDD, so that the stack will leak because of DIBL (Drain induced barrier lowering), However, the middle node Vx settles to a point that each transistor has the same current. If Vx is small, N1 will see a much smaller DIBL effect and it will leak less. As Vx rises, DIBL (Gate to source)
Dynamic Power dissipation in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The CMOS dynamic power is the power dissipated when the logic gate is in the active state. It is mainly due to the switching activity of the i/p signal or mainly due to the charging and discharging of internal node capacitances. Pdynamic = ∝ * CL * (Vdd)^2 * f The CMOS dynamic power (Pdynamic) dissipation is mainly due to The charging and discharging of the load capacitances as the gate switches from one logic to another logic. The short circuit current or leakage current while both PMOS and NMOS stacks are partially ON when not necessary. Activity Factor (∝) The clock gating techniques It will disable the clock to the IDLE portions of the design and hence reducing the power dissipation because of the
Latchup and its prevention in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 Latchup is the most common problem in the CMOS transistor. Mainly causes due to the formation of BJTs (PNP and NPN) and can be prevented using Guard Rings. First of all, this is the most important VLSI interview question. Most of the interview guys prefer to ask this question to check the basics of the candidate regarding MOS and its second-order effects. You must also read these topics which I am listing below. 1. Non-ideal characteristics of MOSFET such as Velocity Saturation, Mobility degradation, Channel length modulation (CLM), body effect, subthreshold conduction, DIBL (Drain induced barrier lowering), BTBT (Band to band tunneling), GIDL (Gate induced barrier lowering), 2. the Tunneling effect, 3. Latchup, 4. Stack effect, 5. Charge sharing effect, 6. Short channel effects, and Narrow channel effects. Latchup: Latchup
Crosstalk and Crosstalk delay effects CMOS by VLSI Universe - April 23, 2020July 21, 20210 In the SI of Physical design, the design will be verified for crosstalk, crosstalk noise, and delays. In the situation when one of the wire switches, the wire will tend to change or affect its neighbor through capacitive coupling. This effect is called Crosstalk. The digital design functionality and its effective performance can be limited by noise. This noise occurs mainly due to the crosstalk with other signals. And it also may occur due to noise on primary inputs or the power supply Vdd. Crosstalk delay effects In the situation when the wire and its neighbor wire are switching simultaneously, the direction in which both are switching will affect the amount of capacitance that must be delivered to the destination and also the
Transistor sizing W/L | CMOS | VLSI CMOS by VLSI Universe - April 23, 2020July 21, 20210 The sizing of the transistor can be done using RC delay approximation. The RC Delay Model helps in delay estimation CMOS circuit. The RC delay model treats the non-linear transistor current-voltage I-V and capacitor voltage C-V characteristics with their equivalent resistance and capacitance model. This RC delay model approximates a transistor as a switch with a series of resistance or effective resistance R (Which is the ratio of the average value of Vds to Ids). The size of a unit transistor is approximated as 4/2 lambda. The RC circuit equivalent models for the PMOS and NMOS transistors are shown below. Here the k width of both PMOS and NMOS transistors is contacted to Source S and drain D. Since the holes in
Method of logical effort | Multi-stage networks CMOS by VLSI Universe - April 22, 2020July 20, 20210 Designing a circuit with great speed or to meet the delay constraints, we need to find the fastest logic function. The optimized implementation of a logic function with great speed is a key task. The method of logical effort is the easiest way to calculate the delay in the MOS circuit. This method specifies the proper number of various logic stages on a path and the appropriate size of the transistor for the gates. Let us see how we can calculate the delay of the circuit and what are parameters we need to know. 1. The delay in a logic gate (d) The delay in a logic gate is mainly due to two components. The parasitic delay (p) and the stage effort/effort delay
