The timing performance of the VLSI or ASICs is checked by either STA Static Timing Analysis or DTA Dynamin Timing Analysis. STA is a technique or method of breaking the circuit into different paths and computing their delay and based on the delayed outcome it validates and verifies the design. let us look into the same.

Also read which were asked in VLSI interviews STA Solved Problems

The main headache of any digital or VLSI design engineer is the timing while designing a CMOS semiconductor chip. How to model it and how to verify the timing. The design team may take a huge amount of time may be spending some months in modifying and making trials to achieve or to meet the required timing specifications met.

This article covers the STA Static Timing Analysis Topic such as setup time and holds time, their violations, and how to check and overcome them, verification of small blocks for the timing, then negative setup and negative hold time, false path, half-cycle, and multi-cycle paths, and the main topic clock gating, etc.

What is Static Timing Analysis? well, you will be able to answer this question once you read this article completely.

In short, STA is one of the best methods or techniques to verify/validate the timing performance of the VLSI/ASICs/Digital design. It is one of the fastest methods available since it checks the design only for the timing without worrying about the functional performance of the design, which makes it fast.

While starting the STA, we need to analyze the design by breaking or dividing into different paths such as Input to Output path (i/p to o/p), input to register path(i/p to reg), Register to Register path(reg to reg), and the register to output path (reg to output).

STA will compute the delays for all the different paths and applies the delay constraint equation (setup and hold checks, etc) and try to improve if any violations.

There is one more approach to verify the timing behavior of the VLSI or digital designs that is DTA (Dynamic Timing Analysis). This approach is rather slow compared to the Static Timing Analysis.

The DTA involves generating the test vectors for the input values to verify the design functionality. This becomes more complex and time-consuming when the number of inputs becomes more than single digits. for example, An n input signal will need 2 power n number of test vectors to be generated.

The DTA Dynamic Timing Analysis does both the functional verification and the timing verification hence it consumes more time compared to STA. And in the STA static timing analysis, the timing analysis of the digital design is performed statically (Therefore the name Static) and it does not depend on the type or number of input data applied.

It won’t involve the process of generating the test vectors for the input to check the working of design, which makes it faster and easier. This is the main reason why the STA Static Timing Analysis becomes more popular and most industries and interviewers prefer to ask questions based on this.

The STA is a full process or complete package to check any VLSI or ASICs or the Digital design to verify all types of timing issues which makes it more Exhaustive. The other types of timing verification approach only verify certain portions of the design and come up with the test vectors or stimulus.

The timing verification through the DTA Dynamic Timing Analysis (or some time it is also referred to as timing simulation) is more difficult as it involves the use of input test vectors to simulate the design. If a circuit contains around 10s to 100 million gates the DTA is a very slow process and we cannot complete the timing verification in time.

On the other hand, the STA provides a very fast and easier way of checking and verifying/analyzing the different paths of the design for any kind of timing violations. In the current situation in building ASIC chips having millions of logic gates a smarter and faster method for timing verification is a must. STA becomes the necessary need for ASIC designers.

In the VLSI CMOS digital design, The design flow mainly involves the steps such as Getting the specification from the customer, Designing a micro-architecture, The design of the RTL, Test bench generation and the functional simulation, Synthesis of the design, Design for testability, The preparation of data for the back end design, Floorplanning, power planning, placement of the standard cells onto the chips, Clock tree synthesis CTS, Routing, DRC and LVS checks, Then the signal integrity to check crosstalk noise effects on the design, and at the end, the design will be sent to the fabrication lab for the tapeout.

They will send back us the GDS2 version of our design. Well in all these steps where exactly we need to do the timing analysis?. The answer to this is given below.

1. At the step RTL design, the STA Static timing analysis is done very rarely since at this stage it is very important to verify the functionality of the design rather than timing. Also, there will be no timing information since the design is still at the initial behavioral level.

2. After the RTL design is synthesized to the gate level the static timing analysis is performed to analyze the design for the worst-case or critical timing paths.

The synthesis stage mainly involves three stages such as Translation, Optimization, and Mapping. After logic optimization, the static timing analysis is applied to check whether the false paths are critical paths that still exist.

3. Next before starting the back end design i.e. PD Physical Design by considering the ideal clock trees with zero delays and zero rise and fall times the static timing analysis is done. And Once the PD starts the STA static timing analysis can be performed to time the design at various stages.

At the backend, time design is done before placement PRE-PLACE, before the clock tree generation PRE-CTC, After the clock tree built POST-CTS, after the routing of signal wires has been done POST-ROUTE, and at last after all the noise and tolerance checks and validation is done POST-SI.