The circuit pitfalls such as Back gate coupling, Threshold power drops, Hot spot, and supply noise are explained. Ignoring these may cause chips to fail.

Back gate coupling

The dynamic logic gates driving multiple i/p static CMOS logic gates are susceptible to the back gate coupling effect. As an example, a dynamic NAND gate driving a static NAND gate is shown in the figure below.

The gate to source capacitance (Cgs1) of the N1 transistor. Let us assume the dynamic NAND logic gate is in evaluation mode and output at node X is floating High. The input of the static NAND logic gate B is initially Low. So the output Y is High. And the internal node W is charged up to VDD – Vth.

For some amount of time node B rises, which discharges Y and W nodes through the N2 transistor, and the source of the N1 transistor falls. This intern tends to bring the gate at node X also fall because of the gate to source capacitance Cgs1 of N1 transistor, resulting in a droop in node X. This depends on the ratio of the gate to source capacitance Cgs1 to the capacitance on node X.

The back gate coupling can be eliminated by driving the input very close to the supply rail VDD and GND. For example, X drove an N2 transistor instead of the N1 transistor.

Threshold power drops

The figure below shows a pass transistor driving and inverter.

The pass transistors are very good at pulling the voltage in a preferred direction but the only swing to within the threshold voltage Vth of the supply rail VDD and GND, that is VDD-Vth or Vth. This is called the threshold drop.

In the above example figure A pass transistor driving the logic 1 into an inverter. The o/p of the pass transistor can only rise to VDD-Vth. and it will be worse than VDD-Vth when the body effect comes into the picture.

This degraded voltage level may become insufficient to completely turn OFF the PMOS transistor of an inverter resulting in static power dissipation. Indeed for the low VDD design, the degraded output level can be so much poor.

These threshold voltage Vth variations are sometimes tolerable in earlier process technologies where VDD was approximately Five times the threshold voltage.

The solution is to replace the PMOS transistor used with the full transmission gates or weak PMOS feedback transistors to pull up the output to VDD.

Hot spots

The performance of the transistor degrades with the increase in temperature, So care must be taken to avoid an excessive number of Hotspots. These hotspots can be caused by the non-uniform power dissipation when the whole power consumption within control.

The distribution non-uniform temperature on the chip leads to variation in the delay between the logic gates across the chip. The chip temperature spots can be generated with the electrothermal simulation.

Power supply noise

The power supplies VDD and GND are not constant across a large chip. Both VDD and GND are subjected to power supply noise mainly caused by IR drop and di/dt noise.

The IR drops are mainly caused by the resistance R of the supply grid between supply pins and the block which is driving a current I. And the di/dt noise occurs across the inductance L as the current I changes rapidly. It is very important for the blocks which are IDLE for every clock cycle and then start witching suddenly.

This power supply noise reduces the performance and also degrades the Noise Margin NM. The NM issue can be resolved by placing the sensitive circuits near each other and allow them to share a common low resistance power wire.
Typically this noise will be in the order of 5 to 10 percent of the VDD.