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Lockup Latches in Testing to fix Hold Failure and Clock Skew

Lockup Latches in Testing to fix Hold Failure and Clock Skew

In the DFT timing analysis, scan chain design of any SOC or an IC VLSI Chip, lockup latches, and lockup registers play a very important role. Especially these are used in fixing hold timing closure as well as to avoid timing clock skew difficulties. Let us understand these from the timing perspective and their significance in congestion. And we will discuss the difference between both lockup registers and lockup latches.


In the current generation of VLSI technology, SOC’s are made of multi-clock domains with various functional sources.
To avoid a large, uncommon path between the clocks of two flip flops from the timing perspective these latches can be the best solution.

But the disadvantage of these lockup latches is that they can cause latch congestion problems. This can be serious when this issue causes after stitching of scan-based design which contains both Embedded Deterministic Test (EDT) and Logic BIST test points.

What are these lockup latches?

Lockup latch is simply a transparent latch (D Latch). These lockup latches are used in scan-based designs, i.e., in between to scan flip flops which have large probability of hold failure. The lockup latches are used to avoid large clock skew problems.
With proper care on the latch polarity (positive latch or negative latch), It can be inserted both in the launching and capturing domain.

An insertion of a lockup latch to avoid clock skew and hold failure

For example, as shown in the above figure the launch flop and capture flops may be of two different domains.
In the scan-based designs (SCAN and SHIFT modes) the two-clock domain interacts with each other and help in shifting the data IN and OUT. It becomes very difficult if there are no lockup latches, as these two domains might not balance properly and cause a large, uncommon path.
This intern may lead to hold time failure and clock skew issues.
A timing analysis STA engineer must think of lockup latches in such cases.

Need for lockup latches in scan-based design.

During VLSI testing, scan stitching of all the sequential elements together in a single scan-based shift register is almost impossible with no timing violation without lockup latches.
These lockup elements help to improve the timing performance such as they provide sufficient timing margin in fixing hold violations. Also, help in getting rid of clock skew issues.

Hold time violation fixing using lockup latches.

There can be two scenarios,
a. Scan-based design chain with two different clock domains
b. Scan-based design chain with two same clock domains but at a very far place i.e. which have more large and uncommon clock paths.

In both above-mentioned cases, there is a great chance that launch flop and capture will have both skew and latency.

A scan-based design with two different clock domains

If the latency of capture flop is greater than the launch flop clock hold check can be as shown in below waveform,
A scan-based design with two different clock domains

But the case when the clock skew difference is very large, it becomes difficult to meet the hold timing without lockup latches. So, this problem can be solved by placing a negative pulse clock lockup latch near the launch flop as shown in the below diagram.

Lockup latch inserted at the launch flop side.

And this case the hold check will be as shown below diagram,

Lockup latch inserted at the launch flop side waveform

Advantages of inserting lockup latches

We can see in the above diagram the hold check is relaxed by a half clock cycle between lockup latch and capture flop with clock domain 2.

First this by inserting lockup latches we can do timing closure for hold failure during SCAN-SHIFT mode. That is the case when there is a large, uncommon path between launch and capture flip flops.

This scenario is AREA efficient and POWER efficient when compared to lockup registers, which will be discussed in the later section.

Role of lockup latches in congestion.

As inserting lockup latch has advantages it also has some disadvantages such as,
These lockup latches in a scan-based design act as breakpoints between the launch and capture flops and hence flops cannot reorder. Because of that, the timing tool will not be able to optimize the length by reordering different scan paths. And hence this leads to longer scan path lengths.

The increase of scan path length in the scan-based design intern causes congestion, which intern leads to an increase of unwanted capacitance between the pins of different flops.

So, there is a need for an approach by which we can reduce the congestion issue caused by lockup latches.

1. One must avoid the use of a large number of lockup latches since they add breakpoints.

2. The scan chain limit must be fixed in such a way that insertion of a lockup latch should be covered within the maximum length.

3. The scan-based designs which use multi-bit flip-flops should not use an ODD number of maximum scan chain length.

4. The scan chains must relate to the physical information so that the flip flops which are far should not get stitched.

Difference between lockup latches and lockup registers.

Both lockup latch and lockup register do serve the same purpose, but they do have some differences. Due to which one is preferred among the other one. Let see who wins the quiz.

Coming to the area perspective a lockup latch is half the size of a lockup register. So, the lockup latch is area efficient compared to the use of lockup registers. Also, we can say that lockup latches are power efficient by considering the same point.

One more difference is where these lockup latches relax the hold timing closure on one side i.e., near launch flop as discussed earlier.

Whereas lockup registers provide skew on both the sides launch and capture. Here lockup latches are preferred as we can afford to have one tap on either side. But registers can be used by tapping the clock from a point to meet setup and hold constraints.

Adding buffers in place of lockup latches

If the timing skew is very large several buffers will be required to compensate the skew. But adding many adders leads to more area requirements. And the same intern allows us to worry about power and area issues.


We can conclude by saying that these lockup latches are the solution to timing closure of hold failure and large clock skews. But with a cost of congestion.
The Congestion issue can be overcome by the above-mentioned approaches.
1. By fixing maximum scan path length.
2. By knowing the proper physical information of the flops on either end.

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