Velocity saturation – Mobility degradation – body effect – CLM CMOS by VLSI Universe - May 5, 2020July 21, 20210 The non-ideal current-voltage effects such as velocity saturation, mobility degradation, body effect, and the channel length modulation CLM are explained. Velocity Saturation At the high lateral electric field Elat that is equal to Vds/L, the velocity of the carrier ceases to increase linearly with the field strength is called Velocity saturation. The velocity saturation results in lower Ids that which is expected at High Vds. Mobility Degradation At high vertical field strengths Evert that is equal to Vgs/tox, the carriers scatter in the oxide SiO2 interface and the process gets slower is called Mobility degradation. Mobility degradation also reduces the current Ids that are expected at high Vgs. Channel length modulation CLM The saturation current Isat of the non-ideal transistor increases with Vds, which is mainly caused by
Synchronizers and Metastability in Digital Logic Circuits CMOS Interview Questions by VLSI Universe - May 5, 2020July 21, 20210 The circuits which accept the input that can change at arbitrary times and produces output with a nonzero probability of Metastability are Synchronizers. The sequential logic elements are mainly characterized by the setup and hold times. If the input data changes before the setup time the output reflects a different new value after a bounded delay. If the input data changes after the hold time the output reflects a different old value after a bounded delay. and If the input data changes between the setup and hold time constraint or aperture then the output may be unpredictable and irrelevant. That is the output may go to a metastable state. Now let us analyze how a Latch will respond to a voltage that will change
DIBL GIDL BTBT and Tunneling effect in CMOS Devices CMOS by VLSI Universe - May 5, 2020July 21, 20210 One must consider these DIBL, GIDL, BTBT, and Tunneling effects while designing in CMOS because these may cause serious issues on the functionality of the design. Understanding these terms is very important in the VLSI design. The PN junctions between diffusion-substrate or diffusion-well will form diodes and also well-substrate junction will be another diode. Because of that, only the substrate and well terminals are connected to the ground or to the supply voltage in PMOS to ensure these diodes will remain to reverse biased but however, these reverse biased diodes will conduct a small amount of current Td and leads to junction leakage. Drain Induced Barrier Lowering (DIBL) DIBL(Drain Induced Barrier Lowering) in MOSFETs leads to a reduction of the Vth of transistors
Interview Experience with Visteon Interview Questions by VLSI Universe - May 5, 2020July 20, 20210 Visteon is an automotive company headquartered in Michigan, United States. In India, its offices are Chennai, Pune, and Bengaluru. My Interview experience at Visteon Visteon visited our college in the first week of November and the process got completed in the third week of the month. The company has allowed all the branches of BTech as well as MTech. It offered the compensation of 8 lack per annum for BTECH and 8.5 lack per annum for MTECH. The profiles offered were Software Profile, Embedded profile, Automotive testing, and validation profile, Audio digital signal processing profile, Machine learning profile, and also deep learning profile. The posting locations were all three Bengaluru, Pune, and Chennai The interview process involved three rounds, Online test The First-round was an online test
Stack effect and Charge sharing problem in Dynamic CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The stack effect is often advantageous (reduces DIBL effect) and whereas Charge sharing is a problem to us (very critical in dynamic and semi-dynamic circuits). Stacking effect in CMOS The leakage through two series OFF transistors is much lower than that of a single transistor because of the Stack effect. The below figure (a) shows two series OFF transistors with their Gate terminals at ZERO volts. The drain of N2 is at VDD, so that the stack will leak because of DIBL (Drain induced barrier lowering), However, the middle node Vx settles to a point that each transistor has the same current. If Vx is small, N1 will see a much smaller DIBL effect and it will leak less. As Vx rises, DIBL (Gate to source)
Dynamic Power dissipation in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The CMOS dynamic power is the power dissipated when the logic gate is in the active state. It is mainly due to the switching activity of the i/p signal or mainly due to the charging and discharging of internal node capacitances. Pdynamic = ∝ * CL * (Vdd)^2 * f The CMOS dynamic power (Pdynamic) dissipation is mainly due to The charging and discharging of the load capacitances as the gate switches from one logic to another logic. The short circuit current or leakage current while both PMOS and NMOS stacks are partially ON when not necessary. Activity Factor (∝) The clock gating techniques It will disable the clock to the IDLE portions of the design and hence reducing the power dissipation because of the
Latchup and its prevention in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 Latchup is the most common problem in the CMOS transistor. Mainly causes due to the formation of BJTs (PNP and NPN) and can be prevented using Guard Rings. First of all, this is the most important VLSI interview question. Most of the interview guys prefer to ask this question to check the basics of the candidate regarding MOS and its second-order effects. You must also read these topics which I am listing below. 1. Non-ideal characteristics of MOSFET such as Velocity Saturation, Mobility degradation, Channel length modulation (CLM), body effect, subthreshold conduction, DIBL (Drain induced barrier lowering), BTBT (Band to band tunneling), GIDL (Gate induced barrier lowering), 2. the Tunneling effect, 3. Latchup, 4. Stack effect, 5. Charge sharing effect, 6. Short channel effects, and Narrow channel effects. Latchup: Latchup
Complete ASIC Design flow 2021 VLSI Design by VLSI Universe - May 4, 2020July 21, 20210 This is the standard VLSI design flow that every semiconductor company follows. The complete ASIC design flow is explained by considering each and every stage. Specification Let us assume we all are IC design engineers, So you are getting the specification from the customer say to design a full adder. For example, the customer says to design a Full adder with 2GHz or 5GHz frequency. So the specification is the first stage in any ASIC design. The specification may be the power or chip area or the chip speed. Microarchitecture design There will be a top-level design engineer in any company that decides the microarchitecture for the specification is whatever given by the customer. He will design the sample architecture which contains for example for a
Important Interview Analog Circuits Answers Analog Interview Questions by VLSI Universe - May 2, 2020July 21, 20210 The section contains analog circuits questions and answers on Resistor networks, transistor MOSFET, current mirror, Opamp, and RC circuits (transient analysis). Answer 1. Answer 2. If RC >> T, then the circuit acts as an integrator. If RC << T, Here the time constant is very small, so the capacitor will be charged very fast and the output voltage almost follows the input voltage. Answer 3. Given a DAC circuit so the value 1010 corresponds to the 10 in decimal and it is 4-bit. Therefore the least significant bit will be equaled to Vred/16 = 8/16 = 0.5V. Hence the value 1010 is 0.5*10 = 5V. One more method by using a superposition theorem also it can be solved. Answer 4. Vthe = 400mV. The
Important Interview Analog Circuits Questions Analog Interview Questions by VLSI Universe - May 2, 2020July 21, 20210 The article contains analog circuits questions and answers on Resistor networks, transistor MOSFET, current mirror, Opamp, and RC circuits. VISIT HERE Click for the solutions 1. Compare the output characteristics of transistor BJT (Bipolar Junction Transistor) and FET (Field Effect Transistor) and also mark the different regions of operations on the characteristics. 2. Given the following RC circuit. Plot the output waveform for the given input based on the given two conditions. τ = RC >> T τ = RC << T 3. For the given DAC(Digital to Analog Circuit) circuit shown in the figure. Calculate the value of Vout for the digital input D3D2D1D0 = 1010. if Vref =8V. 4. Find the minimum value of voltage Vx for which the maximum current flows through
