Verilog always @ posedge with examples – 2021 Verilog by VLSI Universe - June 13, 2021July 21, 20210 Verilog always block (blocking and non-blocking assignments) is explained in detail with examples. Also generation of MUX and Decoders Verilog. In any digital interview, Verilog questions will be asked. Simple questions to confuse and tricky questions will be asked by an interviewer. He will be interested in knowing whether you are very clear with basic concepts or not. Verilog is a hardware description language that makes it necessary to be learned by a digital design aspirant. Questions on blocking and non-blocking assignments, Verilog tasks vs Verilog functions, and Verilog modeling questions based on synthesis are the key concept-oriented ones that are preferred to ask by the interview panel. Well, let us cover some of the important concepts in Verilog HDL. Verilog always block and
Cache memory in detail and hit ratio June 2021 OS concepts by VLSI Universe - June 7, 2021July 21, 20210 In the computer architecture or computer organization (COA), cache memory is a very fast memory, which makes sure the data reach from the main memory to the CPU faster. We will discuss in detail the Cache hit ratio and types of cache memories in OS and The role of cache between CPU and main memory in computer organization and architecture. The cache is nothing but a buffer between CPU and RAM. Parameters like Cache hit, Cache miss, Miss rate, Miss Penalty, Cache block, Cache line, and Cache tag, we will understand all of them to increase the cache performance. We will discuss in detail the cache memory and its working, various types of cache memories, what is cache mapping in memories, and how does
Verilog code for Sine Cos and Arctan Xilinx CORDIC IP core Verilog by VLSI Universe - June 5, 2021July 21, 20210 Generation CORDIC IP core functions for the implementation of trigonometric functions such as sine, cos, and arctan in the Xilinx ISE 14.7. This article helps you to understand the steps to be followed to get a code from Xilinx IP core and run it. The IP core model allows us to select the bit widths for the operation 16bit or 32bit and also the number of iterations. The larger the number of coarse iterations for the CORDIC algorithm, the more will the results accuracy. These IP cores are so accurate and synthesizable codes. One can generate the RTL model and the design summary tables for the implemented CORDIC functions. These are more faster and efficient in the form of hardware complexity and
Verilog code for sine cos and arctan using CORDIC Algorithm Verilog by VLSI Universe - June 3, 2021July 21, 20210 Hardware implementation of trigonometric functions such as sine, cosine and tangent functions using Verilog HDL. Here we make use of CORDIC algorithm to implement these functions in Verilog. It is important to to write a synthesizable code in Verilog to implement on hardware such as FPGA's. The computation of the functions helps to analyze sine wave generation and phase and magnitude calculation of several signals. 1. Basics of CORDIC Algorithm 1.1 Need for CORDIC Algorithm There are several approaches such as the Lookup table method and Polynomial series (for example, Taylor series) to implement these sine, cosine and tangent trigonometric functions. They have complications such as cost of the implementation and the hardware complexity of the design. In case Lookup table method it is fast
Power Calculation and Planning in Physical Design of a VLSI chip VLSI Design by VLSI Universe - June 2, 2021July 21, 20210 Power calculation and planning before any signal routing in the VLSI chip physical design is very important. As Power supply rails carry large transient currents which may distort the signal lines using electrostatic discharge if design rules are not met correctly. Introduction to power planning A VLSI chip in the semiconductor industry is intended to perform a specific operation and has to communicate with the outside world through various signals. To have this signal flow to the chip and out of the chip we need a power supply. Hence proper power planning became an essential part of the planning process in the back-end of the VLSI chip design. An appropriate power supply network must be constructed by considering many aspects such as design
Basics of Memory Testing in VLSI Memory BIST VLSI Design by VLSI Universe - May 30, 2021July 21, 20210 Memory is a very important component in the VLSI Semiconductor industry. In VLSI Circuits' memories play a key role in storing huge data. Memory testing in VLSI using Algorithms and Patterns efficiently is important. Built-in self test, self diagnosis, redundancy analysis and self repair. Various test algorithms which helps in testing of memories such as BIST compiler and BIST for RAM in Seconds. Memory faults and basics of checkerboard algorithm and march tests or algorithm will be discussed. Introduction to Memory Testing In the current situation the world is producing large amount of data which needs to stored in the memories. So memory technology is a growing technology in the semiconductor market. Understanding and improving the memory testing in VLSI is very important
Basics of DFT in VLSI Scan Design and DFMA VLSI Design by VLSI Universe - May 29, 2021July 21, 20210 Let us talk about DFT in VLSI that is, Scan Design for Testing or Design for Testability and it is not Discrete Fourier Transform from Mathematics. Here the main purpose of the DFT Engineers in VLSI is to incorporate some extra logic structure in the design to make the testing easy, cost effective and efficient design for manufacturing and assembly (DFMA). Mainly here we are going to add some DFT testability features to design of a hardware product. After going through this post completely we must be able to answer all the following questions and the same these questions can be asked in VLSI interview. What is DFT in VLSI? Why DFT is used in VLSI? Why DFT is required? What is DFT architecture? What is
Digital Thermometer Code in Verilog VHDL Flash ADC Binary Encoder Verilog by VLSI Universe - May 26, 2021July 21, 20210 Thermometer code to Binary encoder or code converter. A digital thermometer code in VHDL and Verilog, Flash ADC-based Thermometer code with less BER. Introduction A French word thermometer came out in La Recreation Mathematics by J. Leurechon in the year 1924. He comes up with a scale of 8 degrees thermometer. It is very important to have the thermometer digitized. Especially if we implement a thermometer code in Verilog HDL or VHDL, it will be a great job. In the current time, we are using automated logic synthesizers which help us to convert our VHDL or Verilog HDL to a digital circuit easily and faster way. If so, we can adapt different technologies by simply making small changes and by putting constrain on our
Lockup Latches in Testing to fix Hold Failure and Clock Skew STA by VLSI Universe - May 23, 2021July 21, 20210 In the DFT timing analysis, scan chain design of any SOC or an IC VLSI Chip, lockup latches, and lockup registers play a very important role. Especially these are used in fixing hold timing closure as well as to avoid timing clock skew difficulties. Let us understand these from the timing perspective and their significance in congestion. And we will discuss the difference between both lockup registers and lockup latches. Introduction In the current generation of VLSI technology, SOC’s are made of multi-clock domains with various functional sources. To avoid a large, uncommon path between the clocks of two flip flops from the timing perspective these latches can be the best solution. But the disadvantage of these lockup latches is that they can cause
Backgate coupling | Threshold power drops | Hot spots | Supply noise CMOS by VLSI Universe - May 5, 2020July 21, 20210 The circuit pitfalls such as Back gate coupling, Threshold power drops, Hot spot, and supply noise are explained. Ignoring these may cause chips to fail. Back gate coupling The dynamic logic gates driving multiple i/p static CMOS logic gates are susceptible to the back gate coupling effect. As an example, a dynamic NAND gate driving a static NAND gate is shown in the figure below. The gate to source capacitance (Cgs1) of the N1 transistor. Let us assume the dynamic NAND logic gate is in evaluation mode and output at node X is floating High. The input of the static NAND logic gate B is initially Low. So the output Y is High. And the internal node W is charged up to VDD
